In the Ethernet (registered trademark) standard, etc., the data rate is increased from 10 Gbit/s to 25 Gbit/s. Accompanying this, the data rate of the serial data transmission circuit included in the SerDes (SERializer/DESerializer) and the serial data transmission circuit is also increased to 25 Gbit/s.
With reference to FIGS. 1A to 1C, a conventional serial data transmission circuit is explained. FIG. 1A is a diagram illustrating a conventional serial data transmission circuit 101. FIG. 1B is a diagram illustrating a time chart of the serial data transmission circuit 101.
The serial data transmission circuit 101 configured to output serially four digital signals input in parallel has a divide-by-2 frequency divider circuit 110, 2:1 multiplexers 120, 121, and 122, and a driver circuit 130. When driving an output signal at a data rate of 25 Gbit/s, to the divide-by-2 frequency divider circuit 110 and the 2:1 multiplexer 122, a clock signal CK of 12.5 GHz corresponding to a waveform [PA] of FIG. 1B is provided. The divide-by-2 frequency divider circuit 110 divides the frequency of the provided clock signal CK and provides a divide-by-2 signal of 6.25 GHz corresponding to a waveform [PB] of FIG. 1B to the 2:1 multiplexers 120 and 121. The 2:1 multiplexer 120 outputs one of first and third digital signals Din0 and Din2 that are input based the divide-by-2 signal provided from the divide-by-2 frequency divider circuit 110. The digital signal output from the 2:1 multiplexer 120 corresponds to a waveform [PC] of FIG. 1B. Further, the 2:1 multiplexer 121 outputs one of second and fourth digital signals Din1 and Din3 that are input based the divide-by-2 signal provided from the divide-by-2 frequency divider circuit 110. The digital signal output from the 2:1 multiplexer 121 corresponds to a waveform [PD] of FIG. 1B. Furthermore, the 2:1 multiplexer 122 outputs one of the digital signals input from the 2:1 multiplexers 120 and 121 in a clock period CK indicated by 12.5 GHz in FIG. 1A. The digital signal output from the 2:1 multiplexer 122 corresponds to a waveform [PE] of FIG. 1B. Then, an output signal Vout output from the 2:1 multiplexer 122 is transmitted to a transfer path via the driver circuit 130.